FIG. 1 shows a conventional circuit 10 for performing arithmetic operations on one or more floating point operands. Illustratively, each operand has a fixed number of bits i.e., 32, 64, etc. According to standard IEEE format, a 32 bit floating point number has one sign bit, eight exponent bits and twenty three magnitude bits with an implicit bit. If the sign is s, the exponent is e and the magnitude is m, the value of the floating point operand is (-1).sup.s .cndot.m.cndot.2.sup.e-127. The magnitude m is a fractional value with its first non-zero digit aligned with the most significant bit position of the magnitude (unless, as described below, the value of the floating point operand is a special operand value). This property of the magnitude is referred to as normalization. Often, as a result of a calculation, or for purposes of performing a calculation, the first non-zero digit of the value of the magnitude is not aligned with the most significant bit of the magnitude portion of the floating point number. In such a case, the magnitude or floating point number is said to be denormalized. Such a magnitude can be normalized by shifting the decimal place of the value of the magnitude until the first non-zero bit is aligned with the most significant bit position of the magnitude portion of the floating point number and by increasing or decreasing the exponent to indicate the number of bit positions by which the magnitude value has been shifted. IEEE format also provides similar formats for higher precision floating point numbers. Other similar floating point number formats also exist. However, this invention is illustrated herein using the above 32 bit IEEE standard, without loss of generality.
One or more operands x and y are supplied from a memory device, such as a register file 12. The operands x and y are inputted to an arithmetic section 14, which includes a denormalizer and normalizer. The denormalizer equalizes the exponents of the two operands by shifting the decimal point of one operand relative to the other for an addition or subtraction arithmetic operation. The normalizer normalizes the result of the arithmetic operation, which, for example, may have been an addition, a subtraction, a multiplication, or division operation.
Certain mathematical values are not easily represented in the above-described sign, exponent, magnitude format or present difficulty in performing calculations. These mathematical values are zero, infinity and "not a number." For instance, due to constraints on fixed word-sized floating point numbers, it is impossible to represent the value infinity so that it satisfies (-1).sup.s .cndot.m.cndot.2.sup.e-127. On the other hand, although the value zero can be represented so that it satisfies (-1).sup.s .cndot.m.cndot.2.sup.e-127, the number zero can neither be normalized nor denormalized. The IEEE standard provides a single precision format as the following representations for such mathematical values:
(1) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is a zero value, PA1 (2) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a `0` bit followed by a sequence of twenty-two bits, including at least one non-zero bit, to indicate that the result is not a number with signalling (i.e., generation of an error exception), PA1 (3) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a `1` bit followed by sequence of twenty-two bits to indicate that the result is not a number with no signalling, PA1 (4) sign=`1` bit, exponent=a sequence of eight `1` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is negative infinity, and PA1 (5) sign=`0` bit, exponent=a sequence of eight `1` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is positive infinity. PA1 (a) The result is the zero valued special operand if: PA1 (b) The result is the infinity valued special operand if: PA1 (c) The result is not a number if:
Operands that have one of the above-noted bit patterns for representing a respective mathematical value are referred to as "special operands." A denormalized number can also be referred to as a special operand in certain ALU models. For instance, in a "fast" ALU model, a denormalized number can be treated as zero in certain operations. In addition, certain user defined values can be treated as special operands. For example, if the ALU must calculate sin n.pi. (n is an integer) frequently, the bit pattern for n.pi. can be treated as a special operand. Lastly, specific predefined constants, e.g., such as Euler's number can be provided predefined bit patterns. Such bit patterns are also special operands. All other operands are referred to as "ordinary operands."
A special operand generator circuit 22 is provided at the output of the arithmetic section 14 for determining whether or not the result of the arithmetic operation performed in the arithmetic section 14 is a special operand value, and which operand value the result equals.
These are summarized as follows:
(i) the magnitude of the result is zero, or PA2 (ii) a division operation is performed wherein the divisor is infinity and the dividend is zero or a finite number. PA2 (i) a division operation is performed wherein the dividend is infinity but the divisor is not zero, PA2 (ii) a multiplication, addition or subtraction arithmetic operation is performed wherein one operand is infinity, or a division operation is performed wherein the dividend is infinity and the divisor is an ordinary operand, or PA2 (iii) if the result is overflow. PA2 (i) any operation is performed on an operand that is not a number, or PA2 (ii) any invalid operation is performed such as the square root of a negative number, a division operation is performed wherein both the dividend and divisor are zero or the dividend is infinity and the divisor is zero, etc.
When the arithmetic section 14 performs one of the operations listed above that results in a value other than an ordinary operand value, the arithmetic unit outputs a signal indicating that the result is zero, infinity or not a number to the generator circuit 22. In response, the circuit 22 generates the appropriate output floating point number as per the above noted IEEE standard of special operands set.
Note that often the result of the arithmetic calculation can be determined without actually performing all of the ordinary steps of the arithmetic calculation when one or more of the operands is a special operand. See, e.g., MANO, COMPUTER ARCHITECTURE sec. 10-4, p. 377-387 (1982). Many of these results are noted above. In addition to these, suppose a first operand is to be added to a second operand or the first operand is to be subtracted from the second operand. If the first operand is the zero valued special operand, then the result must be equal to the second operand. Likewise, if the first operand is to be subtracted from the second operand and the second operand is the zero valued special operand, the result must have a magnitude and exponent that equal the magnitude and exponent of the first operand and a sign of opposite polarity as the second operand.
Interposed between the register file and the arithmetic section 14 are detectors 24 and 26. One detector 24 or 26 is provided for each operand input path. The detectors 24 and 26 each receive a respective operand x or y and determines whether or not the received operand represents a special operand. If not, the detector 24 or 26 simply outputs the operand x or y to the arithmetic section 14. However, if the detector 24 or 26 detects that the operand x or y represents a special operand, the detector 24 or 26 identifies the type of the operand--the detector determines which of the special operands the received operand x or y represents. The detector 24 or 26 then outputs an indication of the type of the operand to the arithmetic section 14. As a result, the arithmetic section 14 generates the appropriate result using fewer steps as would normally be necessary. For instance, two ordinary operands are added (subtracted) by normalizing the operand with the smaller exponent relative to the operand with the larger exponent, adding (subtracting) the magnitudes of the two operands, e.g., using a carry look-ahead or carry save adder, and then normalizing the result. See U.S. Pat. No. 4,758,974. Likewise, two ordinary operands are multiplied (divided) by multiplying (dividing) the magnitudes of the two ordinary operands, e.g., using a Booth multiplier, adding (subtracting) the exponents of the two operands and then normalizing the result. The detectors 24, 26 cause the arithmetic section 14 to avoid performing such steps (which would either be impossible, erroneous or simply time consuming) and instead to generate control signals (exp.sub.-- sel, mag.sub.-- sel) and/or result sign (result.sub.-- sgn), magnitude (result.sub.-- mag) and exponent (result.sub.-- exp) as per the predetermined rules set forth above.
FIG. 2 shows an exemplary special operand generator circuit 22 in greater detail. As shown, the special operand generator circuit 22 includes first and second multiplexers 222 and 224. The first multiplexer 222 has a first input receiving a sequence of eight `0` bits, a second input receiving a sequence of eight `1` bits and a third input receiving an exponent that is outputted from the arithmetic section 14. The first multiplexer 222 also receives selector control signals exp.sub.-- sel from the arithmetic section 14. The second multiplexer 224 has a first input receiving a sequence of twenty-three `0` bits, a second input receiving a sequence including a first `0` bit followed by a sequence of twenty-two bits that have at least one non-zero bit, a third input receiving a sequence including a `1` bit followed by sequence of twenty-two bits and a fourth input receiving the magnitude outputted from the arithmetic section 14. The second multiplexer 22 also receives selector control signals mag.sub.-- sel from the arithmetic section 14.
The arithmetic section 14 outputs appropriate selector control signals exp.sub.-- sel, mag.sub.-- sel to the multiplexer 222 to output a resulting exponent, and to the multiplexer 224 to output a resulting magnitude of an arithmetic operation. The sign bit result.sub.-- sgn is separately outputted from the arithmetic section 14 and appended to the exponent and magnitude outputted from the multiplexers 222 and 224. When the result of an arithmetic operation is zero, the arithmetic section outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `0` bits for the exponent and twenty-three `0` bits for the magnitude. When the result of an arithmetic operation is infinity, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `1` bits for the exponent and the twenty-three `0` bits for the magnitude. When the result of an arithmetic operation is not a number with signalling, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting eight `1` bits for the exponent and the `0` bit followed by twenty two bits including at least one `1` bit as the magnitude. Likewise, when the result of an arithmetic operation is not a number without signalling, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `1` bits as the exponent and the `1` bit followed by twenty-two bits as the magnitude. In all other cases, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the exponent and magnitude generated in the arithmetic section 14 as the result exponent and magnitude.
FIG. 3 shows a conventional detector 24 or 26. As shown, the detector 24 or 26 includes two comparator circuits 252 and 254. The comparator 252 receives the exponent (x.sub.-- exp or y.sub.-- exp) of the inputted operand x or y and compares it to a sequence of eight `0` bits and a sequence of eight `1` bits. If the exponent is the same as the sequence of eight `0` bits, the comparator 252 outputs a logic `1` bit on the line 255. If the exponent is the same as the sequence of eight `1` bits, the comparator 252 outputs a logic `1` bit on the line 256. In all other circumstances, the comparator 252 outputs logic `0` bits on the lines 255 and 256. The comparator 254 receives the magnitude (x.sub.-- mag or y.sub.-- mag) of the inputted operand x or y and compares it to the sequence of twenty-three `0` bits. If the magnitude is the same as the sequence of twenty-three `0` bits, the comparator 254 outputs a logic `1` bit on the line 257. If not, the comparator 254 outputs a logic `1` bit on the line 258.
Three AND gates 261, 262 and 263 are also provided. The AND gate 261 receives as inputs the logic bits outputted on the lines 255 and 257. The AND gate 261 therefore outputs a signal indicating whether or not the operand represents a zero valued special operand (a logic `1` indicating that the operand represents the zero valued special operand). The AND gate 262 receives as inputs, the logic bits outputted on the lines 256 and 257. The AND gate 262 therefore outputs a signal indicating whether or not the operand represents infinity (either negative or positive) (a logic `1` indicating that the operand represents the infinity valued operand). The AND gate 263 receives as inputs the logic bits outputted on the lines 256 and 258. The AND gate 263 therefore outputs a signal indicating whether or not the operand represents a non-number special operand (with or without signalling) (a logic `1` indicating that the operand is a non-number special operand). Each of the signals outputted by the AND gates 261-263 of the detectors 24 and 26 are inputted to the arithmetic section 14. Illustratively, the arithmetic section 14 has combinatorial logic for translating these signals, and possibly the values of the operands, to the outputted exponent and magnitudes and control signals exp.sub.-- sel and mag.sub.-- sel provided to the generator circuit 22 of FIGS. 1 and 2. See, e.g., Joseph J. F. Cavanagh, Digital Computer Arithmetic Design and Implementation, p.384.
A disadvantage of the architecture shown in FIGS. 1-3 is that detectors 24 and 26 must be provided in the input path of each operand to determine whether or not the operand represents a special operand, and if so, which special operand value is represented. A detector is necessary because nearly all of the bits of the operand must be examined to determine if the operand represents a special operand value. This introduces a latency into the arithmetic processing of the calculation circuit 10.
It is an object of the invention to overcome the disadvantages of the prior art.